Field of the Invention
The present invention relates to an integrated semiconductor circuit having NMOS transistors which are at an increased operating voltage in a corresponding operating mode.
Integrated semiconductor circuits often have programmable elements for permanently storing data. In the case of integrated memory circuits, these may be in particular, electrically programmable elements which, by way of example, serve for storing repair information with regard to repairing defective memory cells. The programmable elements can be programmed at the end of the process for fabricating the integrated circuit by an application of a so-called burning voltage.
For the purpose of programming the electrically programmable elements, a burning voltage having a high potential level is applied to the circuit in a corresponding operating mode, for example externally or internally by an additional circuit. The operation for programming the programmable elements is in this case effected by a high voltage or a high current, which leads to permanent alteration of the conductor track resistance, for example causing a corresponding electrical fuse to melt or an insulator to break down (so-called anti-fuse).
As a result of the burning voltage being applied to a circuit for programming a programmable element, high potential differences occur across the circuit and, in some instances, across other circuits connected thereto. In order to withstand the potential differences, which are considerably increased in comparison with unaffected circuit sections of the integrated circuit, it is necessary for those circuit elements of the relevant circuit which are at the increased voltage to be given adequate dimensions. With the application of recent technologies with decreasing feature sizes and smaller gate oxide thicknesses, it is generally no longer possible to configure the affected circuit elements such that they can withstand the increased potential difference.
Integrated semiconductor circuits often contain transistors using NMOS technology. NMOS transistors are usually made in a substrate with a base doping of a p-conductivity type. Accordingly, it contains zones with drain terminals and source terminals with a respective doping of an n-conductivity type and also a channel with a gate terminal. Situated in the substrate beneath the channel there is often a fourth terminal of the transistor, which is also referred to as a bulk terminal. The substrate in which the NMOS transistor is made is usually connected to a fixed reference-ground potential of the integrated circuit. If the transistor is not electrically insulated from the rest of the substrate of the integrated circuit, its bulk terminal is, accordingly, likewise at the reference-ground potential. If, for example, the burning voltage mentioned above is applied to one of the other 10 terminals of the transistor, the transistor may incur permanent damage on account of the increased potential difference between the corresponding terminal of the transistor and the bulk terminal thereof. The semiconductor circuit generally manifests a functional error as a consequence.
It is accordingly an object of the invention to provide an integrated semiconductor circuit with an increased operating voltage that overcomes the above-mentioned disadvantages of the prior art devices of this general type, which contains a transistor of the NMOS type and protects against damage, the transistor which is at an increased input voltage or supply voltage in a corresponding operating mode.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated semiconductor circuit containing a substrate of a p-conductivity type. A well of the p-conductivity type is disposed in the substrate and electrically insulated from the substrate, and the well also has a well terminal. An NMOS transistor is disposed in the well. A control circuit having a terminal for an output signal whose potential can be altered by the control circuit is provided. The terminal for the output signal is connected to the well terminal.
The integrated semiconductor circuit has a transistor of the NMOS type that is disposed in the well of the p-conductivity type, which well, for its part, is disposed in the substrate of the p-conductivity type. The well is electrically insulated from the substrate, this being achieved during fabrication for example by a so-called buried well process. The semiconductor circuit furthermore has a control circuit with an output signal whose potential can be altered by the control circuit. A well terminal of the well is connected to the output signal of the control circuit. The well terminal forms the bulk terminal of the transistor. The provision of the control circuit thus makes it possible to influence the potential of the well (bulk potential) in such a way that the potential difference between the well and the remaining terminals of the transistor is small enough to protect the transistor against damage.
As a result of the deliberate intervention in the bulk potential of transistors, there is no need for any additional individual protective circuits for each transistor or additional process steps which additionally increase the outlay for fabricating an integrated semiconductor circuit. Furthermore, it is possible, within an integrated semiconductor circuit, to operate different circuit regions with a different reference-ground potential and a different operating voltage. The potentials of the different circuit regions are completely decoupled from one another. By deliberately influencing the potential difference between the bulk terminal and the remaining terminals of a transistor, it is possible, moreover, to use, even in the circuit regions which are at a higher operating voltage, the circuit elements of the same type which are employed in the remaining circuit regions. This simplifies the configuration and construction process for an integrated circuit.
In a refinement of the invention, the semiconductor circuit has a first operating mode and a second operating mode. In the first operating mode, a first potential of an operating voltage is applied and the output signal of the control circuit has a first reference-ground potential. In the second operating mode, a second potential of an operating voltage is applied, the second potential being higher than the first potential, and the output signal of the control circuit has a second reference-ground potential, which is higher than the first reference-ground potential. Thus, by way of example, if a burning voltage for programming an electrical fuse is applied to the semiconductor circuit in the second operating mode, by virtue of the bulk potential of the NMOS transistor being raised to a suitable extent during the burning operation, the control circuit prevents an excessively high potential difference from occurring across the transistor.
In a development of the invention, the semiconductor circuit or circuit sections thereof can be operated in its or their intended function exclusively in the first operating mode. It contains a differential amplifier, for example. The various configurations of differential amplifiers have, in principle, the same basic circuit of the known type. This contains two input transistors, a current source and an active or passive load. A potential difference between the input signals present at the two input transistors brings about a change in potential at an output of the differential amplifier. The input transistors are embodied using NMOS technology. In comparison with PMOS transistors, these generally have a higher gain and require less space. If an increased input signal or potential of an operating voltage compared with the first operating mode is applied to the control terminal of one of the input transistors in the second operating mode, an increased potential difference between the control terminal and the bulk terminal of the transistor is reduced by the output signal of the control circuit.
Furthermore, an increased potential difference occurs between the control terminal of the transistor and the circuit node at which the input transistors are connected to the current source. In order to reduce this potential difference as well, the current source is switched off in the second operating mode and the circuit node is connected to the output signal of the control circuit.
The advantage of protection realized in such a way is that there is no need for a further protective circuit for protecting the input transistor. The further protective circuit for example having an ESD-like structure and thus constituting a low-resistance protection. In this embodiment, the input resistance of the differential amplifier remains at a high value, and so the power loss remains low.
In a further development, the semiconductor circuit or circuit sections thereof can be operated in its or their intended function in both operating modes. It has, by way of example, an inverter stage having a switching transistor of the NMOS type whose bulk terminal and source terminal are connected to one another. As a result, both the bulk potential and the source potential are raised to a suitable extent by the control circuit in the second operating mode. In order to ensure the intended function of the inverter stage in the second operating mode as well, the semiconductor circuit has a further control circuit, e.g. embodied as a so-called level shifter, which correspondingly raises a signal level of an applied input signal. The output signal of the further control circuit that can thus be picked off is connected to an input signal of the inverter stage. As a result, in addition to the supply potential and the reference-ground potential of the inverter stage, the signal level of the input signal of the inverter stage is also raised correspondingly. The relative potential differences in accordance with the first operating mode, which corresponds to normal operation for example, are thereby preserved.
With the foregoing and other objects in view there is further provided, in accordance with the invention, an integrated semiconductor circuit containing a substrate of the p-conductivity type. Wells of the p-conductivity type are disposed in the substrate and electrically insulated from the substrate, and the wells each have a well terminal. A control circuit having a terminal for an output signal whose potential can be altered by the control circuit is further provided.
The terminal for the output signal is connected to the well terminal. A differential amplifier is provided which has two NMOS input transistors disposed in the wells and connected to each other. A current source is connected to the two NMOS input transistors and defines a circuit node at a connection point between the two NMOS input transistors and the current source. The circuit node is connected to the terminal for the output signal of the control circuit in the second operating mode, and the current source is switched off in the second operating mode. The differential amplifier further has a load element connected to the two input transistors. A first potential of an operating voltage is applied to one of the two input transistors in a first operating mode. A second potential of the operating voltage is applied to the one of the two input transistors in a second operating mode, the second potential being higher than the first potential. The output signal of the control circuit has a first reference-ground potential in the first operating mode, and the output signal of the control circuit has a second reference-ground potential in the second operating mode, the second reference-ground potential being higher than the first reference-ground potential.
With the foregoing and other objects in view there is also provided, in accordance with the invention, an integrated semiconductor circuit containing a substrate of a p-conductivity type. A well of the p-conductivity type is disposed in the substrate and electrically insulated from the substrate and the well has a well terminal. An inverter stage having an input terminal for an input signal and at least one NMOS switching transistor is disposed in the well. The NMOS switching transistor has a source terminal that is connected to the well terminal. A first control circuit having a terminal for an output signal whose potential can be altered by the control circuit is provided. The terminal for the output signal is connected to the well terminal. A second control circuit having a terminal for an input signal and a terminal for an output signal is provided. The second control circuit raises a potential of the input signal in the second operating mode, which, in a raised state, can be picked off at the terminal for the output signal of the second control circuit. The input terminal for the input signal of the inverter stage is connected to the terminal for the output signal of the second control circuit. A first potential of an operating voltage is applied to the semiconductor circuit in a first operating mode. A second potential of the operating voltage is applied to the semiconductor circuit in a second operating mode, the second potential being higher than the first potential. The output signal of the first control circuit has a first reference-ground potential in the first operating mode, and the output signal of the first control circuit has a second reference-ground potential in the second operating mode, the second reference-ground potential being higher than the first reference-ground potential.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in an integrated semiconductor circuit with an increased operating voltage, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.